Enabling Next Generation High Performance
Networking & Communication Applications
Networking & Communication Applications
QDR Applications
How QDR SRAMs help enable the evolution of next generation Networks:
In the networking world, Routers and Switches are devices that forward data packets across computer networks. Routers perform the data "traffic directing" functions on the Internet. A router is connected to two or more data lines from different networks. When data comes in on one of the lines, the router reads the address information in the packet to determine its ultimate destination. Then, using information in its routing table, it directs the packet to the next network on its journey or drops the packet. A data packet is typically passed from router to router through the networks of the Internet until it gets to its destination computer unless the source IP is on a private network.
The routers and switches deal with a sequence of random packets that need to be routed or switched to destinations dictated by their header fields after appropriate security checks and classification. Each packet requires 15-25 memory transactions to random locations before it is routed from the ingress to an egress of the router/switch.
QDR SRAMs are used in the Data Plane memory of Line Cards in edge and core routers for assisting the Network Processor and Traffic Manager in performing activities such as Statistics Measurements, Packet Buffering, Flow State Control, and Traffic Scheduling. The major performance bottleneck in routers is not the switching speed but actually the time taken to examine the packet header in order to determine its type and destination, look up the route in the forwarding table, classify the packet for scheduling, and update various statistics and state counters. All of these tasks require memory and hence the speed of the memory interface can dictate the speed of the data path.
Packet Buffer: Each line card on the router has an ingress buffer (or input port) and egress buffer (or output port). The input port or ingress buffer is the point of attachment for the physical link and point of entry for incoming packets. The output port or egress buffer stores packets and schedules them to dispatch to the switch fabric. The higher the line rate, the greater the needs of the packet buffer. QDR SRAMs can help address packet buffer applications, where customers use head/tail caching to complement DRAM.
Forwarding Information Base (FIB) Look Up Table: The FIB table stores the potential destination addresses of the next hop in the route. The look up is an iterative process and therefore involves multiple accesses to the memory. Each packet of data will require between 4 and 8 random accesses to the memory. Therefore, the QDR SRAMs are the memory of choice for table look up applications.
Packet classification or Access Control Limitation (ACL): This is a processing step to examine the characteristics of the incoming packets (e.g. a five tuple comprised of source address, destination address, source port, destination port, and protocol), and make decisions on whether or not to allow the packet through. Once the packet has been classified or policed it is temporarily stored in a buffer subsystem for scheduling. QDR SRAMs can be used for ACL if algorithmic search is used instead of random search.
Scheduling: Scheduling is the process of deciding when to send a packet onto the switch fabric and is determined based on the destination of the packet and Quality of Service (QoS) or Class of Service (CoS) required. Packets are grouped into several classes, each of which relate to a tiered service offering (revenue segment for service providers). Typically the scheduling application requires 1R +1W per packet, and therefore is less demanding in terms of RTR. For 100Gbps line card rates, scheduling can be serviced by QDR SRAMs
Statistics & Flow States (both implemented in single memory): Routers maintain statistics on a per packet and per flow (stream of related packets) basis. This is accomplished in the form of counters. Each application can have as much as six counters. The counters are used to store information on prefix, flows, and packet classification. Hence counters have to be high performance memories that can accommodate multiple R/M/W operations in a second. Flow/State counters share the same memory foot print as that of statistics counters. QDR SRAMs in a line a card can be shared for Statistics and Flow/States.
The number of random transactions required increases linearly with line rate for all of the applications described above. Hence Random Transaction Rate(RTR)* is a critical parameter for all of the applications with the exception of packet buffer. As customers migrate to higher line card rates (100GbE and beyond), the RTR requirements accordingly and necessitate memories with higher RTR performance which can meet the demands of higher line rate systems.
* Random Transaction Rate is the number of fully random memory accesses (reads or writes) that can be performed on the memory and is currently one of the major limiting factors for the continued increase in networking line and switching rates. Simply stated it is the rate at which random data can be addressed (or random address rate).This metric is independent of the number of bits being accessed for the transaction (transaction bit width). RTR would be measured in million transactions per second or MT/s.
A comparison of RTR performance across different memory technologies is show below:
For networking functions like statistics, flow states and scheduling, the memory subsystem needs to support a read and a write operation to the same data structure leaving only SRAM memories as the optimal option for supporting these read/write networking functions.
How QDR SRAMs help enable the evolution of next generation Networks:
In the networking world, Routers and Switches are devices that forward data packets across computer networks. Routers perform the data "traffic directing" functions on the Internet. A router is connected to two or more data lines from different networks. When data comes in on one of the lines, the router reads the address information in the packet to determine its ultimate destination. Then, using information in its routing table, it directs the packet to the next network on its journey or drops the packet. A data packet is typically passed from router to router through the networks of the Internet until it gets to its destination computer unless the source IP is on a private network.
The routers and switches deal with a sequence of random packets that need to be routed or switched to destinations dictated by their header fields after appropriate security checks and classification. Each packet requires 15-25 memory transactions to random locations before it is routed from the ingress to an egress of the router/switch.
QDR SRAMs are used in the Data Plane memory of Line Cards in edge and core routers for assisting the Network Processor and Traffic Manager in performing activities such as Statistics Measurements, Packet Buffering, Flow State Control, and Traffic Scheduling. The major performance bottleneck in routers is not the switching speed but actually the time taken to examine the packet header in order to determine its type and destination, look up the route in the forwarding table, classify the packet for scheduling, and update various statistics and state counters. All of these tasks require memory and hence the speed of the memory interface can dictate the speed of the data path.
Packet Buffer: Each line card on the router has an ingress buffer (or input port) and egress buffer (or output port). The input port or ingress buffer is the point of attachment for the physical link and point of entry for incoming packets. The output port or egress buffer stores packets and schedules them to dispatch to the switch fabric. The higher the line rate, the greater the needs of the packet buffer. QDR SRAMs can help address packet buffer applications, where customers use head/tail caching to complement DRAM.
Forwarding Information Base (FIB) Look Up Table: The FIB table stores the potential destination addresses of the next hop in the route. The look up is an iterative process and therefore involves multiple accesses to the memory. Each packet of data will require between 4 and 8 random accesses to the memory. Therefore, the QDR SRAMs are the memory of choice for table look up applications.
Packet classification or Access Control Limitation (ACL): This is a processing step to examine the characteristics of the incoming packets (e.g. a five tuple comprised of source address, destination address, source port, destination port, and protocol), and make decisions on whether or not to allow the packet through. Once the packet has been classified or policed it is temporarily stored in a buffer subsystem for scheduling. QDR SRAMs can be used for ACL if algorithmic search is used instead of random search.
Scheduling: Scheduling is the process of deciding when to send a packet onto the switch fabric and is determined based on the destination of the packet and Quality of Service (QoS) or Class of Service (CoS) required. Packets are grouped into several classes, each of which relate to a tiered service offering (revenue segment for service providers). Typically the scheduling application requires 1R +1W per packet, and therefore is less demanding in terms of RTR. For 100Gbps line card rates, scheduling can be serviced by QDR SRAMs
Statistics & Flow States (both implemented in single memory): Routers maintain statistics on a per packet and per flow (stream of related packets) basis. This is accomplished in the form of counters. Each application can have as much as six counters. The counters are used to store information on prefix, flows, and packet classification. Hence counters have to be high performance memories that can accommodate multiple R/M/W operations in a second. Flow/State counters share the same memory foot print as that of statistics counters. QDR SRAMs in a line a card can be shared for Statistics and Flow/States.
The number of random transactions required increases linearly with line rate for all of the applications described above. Hence Random Transaction Rate(RTR)* is a critical parameter for all of the applications with the exception of packet buffer. As customers migrate to higher line card rates (100GbE and beyond), the RTR requirements accordingly and necessitate memories with higher RTR performance which can meet the demands of higher line rate systems.
* Random Transaction Rate is the number of fully random memory accesses (reads or writes) that can be performed on the memory and is currently one of the major limiting factors for the continued increase in networking line and switching rates. Simply stated it is the rate at which random data can be addressed (or random address rate).This metric is independent of the number of bits being accessed for the transaction (transaction bit width). RTR would be measured in million transactions per second or MT/s.
A comparison of RTR performance across different memory technologies is show below:
For networking functions like statistics, flow states and scheduling, the memory subsystem needs to support a read and a write operation to the same data structure leaving only SRAM memories as the optimal option for supporting these read/write networking functions.