Enabling Next Generation High Performance
Networking & Communication Applications
Networking & Communication Applications
Abridged Specs
QDR II + Xtreme
QDR II+ Xtreme SRAMs are Fit, Form, Function, Compatible with existing QDRII+/DDRII+. They are an extension to the QDRII+/DDRII+ product Family
Density Options: 36Mb, 72Mb
QDR II + Xtreme
QDR II+ Xtreme SRAMs are Fit, Form, Function, Compatible with existing QDRII+/DDRII+. They are an extension to the QDRII+/DDRII+ product Family
Density Options: 36Mb, 72Mb
Features:
633 MHz clock for Burst 4 operation
450MHz clock for Burst 2 operation
QDR; Separate independent read and write data ports
Supports concurrent transactions
DDR; Common I/O Interface
2.5 cycle latency
Two input clocks (K and K) for precise DDR timing
Echo clocks (CQ and CQ) simplify data capture
Data valid pin (QVLD) to indicate valid data on the output
On-Die Termination (ODT) feature
Supported for D[x:0], BWS[x:0], and K/K inputs
Single multiplexed address input bus latches address inputs for read and write operations
Separate port selects for depth expansion
Synchronous internally self-timed writes
Available in x18, and x36 configurations
Full data coherency, providing most current data
Core VDD = 1.8V± 0.1V; IO VDDQ = 1.4V -1.6V
HSTL inputs and variable drive HSTL output buffers
Available in 165-Ball FBGA package
72M and lower densities (13x15x1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 compatible test access port
Phase Locked Loop (PLL) for accurate data placement